Validation of Multiprocessor Multithreaded Architectures

Dedicated to micro-nano technologies and embedded software for systems on chip, the French pôle de compétitivité mondial project Minalogic-Multival addresses verification and performance evaluation issues for three innovative asynchronous system architectures developed by Bull, CEA-Leti, and ST Microelectronics. These architectures are highly parallel and require dedicated and intricate communication protocols. No industrial solution exists by now to guarantee or even estimate the interplay of functional and performance properties of such systems. Within this industrial project, compositional performance evaluation techniques developed by us play a central role. Holger Hermanns is by now an invited professor at INRIA Rhone-Alpes, and a part-time expert member of the Multival project. The project is unique in responding to critical demands by the industrial manufacturers, facing concurrency and performance challenges of a new kind.

Recent achievements of the Dependable Systems and Software chair in this context are on the project page at